Title :
Evaluation of MOS technologies by measurements
of conduction and ground noise. Application in the hardening
|
This report
is dedicated to the evaluation of MOS technologies by measures of conduction
and ground noise.
The
developed techniques of measure were tested on various technologies of
manufacture of CMOS components on massive silicon or of TFT (Thin Film
Transistor) type on amorphous silicon.
From the
equations of functioning of capacities and MOS transistors, a methodology of
characterization of these structures allowed to extract a set of electric and
geometrical parameters reporting in a satisfactory way the functioning of the
component. These parameters are also representative of the used technology and
allow so to qualify the process of manufacture.
On the
fundamental plan, the study of the electric noise allowed to clarify the
origin of the 1/f noise and to put in evidence new sources of noise
connected to the phenomena of conduction proper to the transistors of geometry
of submicronic grid.
On the
practical plan, the electric noise was used to qualify the MOS technologies.
It allows to show the role
played by the parasite elements inherent to these technologies. Being a not
destructive mean of investigation, the ground noise also allowed to put in
evidence a correlation between the 1/f noise presented by MOS transistors
before irradiation and the evolution of their conduction's parameters after irradiation.
|
|
MOS Capacities, MOS Transistors, Thin Film Transistors,
1/f noise, Random Telegraph Signal, Low Frequencies, Radiation Co-60,
Hardening.
|
|
|